In general, to be able to read a non-volatile memory cell it is necessary to make a comparison of the current of this memory cell with a reference current. This operation is performed by a circuit defined as a sense amplifier. The reference current is generated by a reference memory cell, for example. Using a current mirror array, this generates a current during each reading, which lies in the middle between the value of the current corresponding to a programmed cell and that of an erased cell. To reduce the consumption current, it is conceivable to reduce the reference current injected into the sense amplifiers. However, a drawback of this method is that the reading access time is increased.
Reading a non-volatile memory such as a NOR flash memory, for example, consumes a static current for as long as the sense amplifier is in operation. This represents another drawback, since the power consumption of such a reading device remains relatively significant particularly in the case when the frequency of memory access by a microprocessor unit decreases.
A non-volatile memory device such as a flash memory is described in the patent document U.S. Pat. No. 6,301,156. This device allows execution of a program verification based on a change in charged or discharged current of capacitors connected to a bit line of a memory cell to be read and a bit line of a reference cell. A sense amplifier allows the output signals of the memory cell network to be compared with the output signals of the reference cell. This sense amplifier thus allows detection of a difference in potential of the charge rate of each capacitor output from the network and output from the reference cell to determine a state of a selected memory cell.
However, a major portion of the electronic components of the memory device of this patent U.S. Pat. No. 6,301,156 remains in operation during each verification or read cycle, and this represents a drawback.
In contrast, patent document US 2005/0169078 describes a reading device for a memory network, which comprises means to reduce the read time during a read cycle controlled by a microprocessor unit. For this purpose, it comprises time-lag means for the read time in each read cycle initiated by the microprocessor unit. The time-lag means comprise a dummy memory network linked to a reference sense amplifier, which supplies a latch signal to a latch register. This latch register receives data from a selected cell to be read via a sense amplifier. At the end of the read time of all valid data, the latch signal allows the latch register to be closed to retain the data read as output. This latch signal also allows the disconnection of all the sense amplifiers to be controlled before a subsequent read request.
However, in this patent document US 2005/0169078, the read time is not precisely determined in order to reduce the power consumption as far as possible, because the charge of the dummy cell network is not well defined.